1. Field of the Invention
The present invention relates to a semiconductor integrated circuit apparatus using a dielectric separation substrate, and more particularly to a semiconductor integrated circuit apparatus having high withstand voltage and high integration density.
2. Description of the Prior Art
A dielectric separation substrate having a high withstand voltage and capable of downsizing the region for separating elements is presently used as a substrate for semiconductor integrated circuits dealing with high voltages, instead of a pn separation method. An existing dielectric separation substrate has the constitution wherein semiconductor islands such as n-type semiconductor islands, each of which are surrounded by oxide films (SiO.sub.2) are embedded together in one side of a supporter. The supporter includes poly-silicon and high impurity concentration layers (n+) formed along with the oxide film at the places adjoining other islands for suppressing the elongation of a depletion layer. This existing dielectric separation substrate has the following problems.
The first problem is one related to product processing. The substrate producing process comprises the steps of;
{1}forming V character form grooves on one side of a n-type semiconductor substrate by the anisotropic etching using a mixture of potassium hydroxide(KOH), water and N-propanol, PA1 {2}injecting impurities to make the n+ layers on the faces of the grooves and the side of the semiconductor substrate, PA1 {3}forming oxide films on the faces of the grooves and one side of the semiconductor substrate, PA1 {4}accumulating poly-silicon on the oxide films, and PA1 {5}chipping down the other side of the semiconductor substrate to the bottom of the grooves and forming the semiconductor islands separated by the oxide films. PA1 {1}It is possible to reduce the area of a semiconductor island and attain high integration density due to the decrease of the field strength at the surface of the semiconductor island. PA1 {2}It is possible to reduce the area of a semiconductor island and attain high integration density due to the considerable decrease of the depth of a semiconductor island by the extension of the depletion layer beyond the insulating film into the supporter. PA1 {3}It is possible to decrease the field strength at the surface of the semiconductor island and attain the high withstand voltage by the extension of the depletion layer beyond the insulating film into the supporter. PA1 {4}It is possible to provide a simplified production process of a dielectric separation substrate due to the considerable decrease of the depth of the semiconductor islands.
The above-mentioned producing process of the dielectric separation substrate has the first problem that the producing process is not easy since it is necessary to form a thick poly-silicon layer. The second problem is that the element integration density decreases in accordance with an increase of the withstand voltage. It is needed to enlarge the region of the depletion layer for increasing the withstand voltage, which requires the formation of deep semiconductor islands. Since the side face of the semiconductor island makes an angle of 55.degree. to its exposed face due to the above-mentioned anisotropic etching, the area of the exposed face becomes larger and the integrated density decreases as the depth of the semiconductor island increases.
One dielectric separation substrate which solves the first problem is described in a Japan Patent Laid Open 292934/1986. The dielectric separation substrate has the constitution wherein the semiconductor islands are made more shallow, the poly-silicon layer is formed a little thicker so that it can bury the grooves and a semiconductor substrate having a oxide film on its surface is formed on the poly-silicon layer. By this constitution, the producing process becomes easier since accumulation of the deep poly-silicon is not needed. However, this dielectric separation substrate has the defect that the integration density considerably decreases in accordance with an increase of the withstand voltage, which is explained by FIG. 18.
In FIG. 18, a semiconductor island 100, a poly-silicon layer 101 in which the semiconductor island 100 is buried and supported by a silicon oxide film 102, and a semiconductor substrate 103 adhered to the poly-silicon layer 101 with a silicon oxide film 104 between, etc. are shown. In the case of a diode, the semiconductor island 100 includes a n- type region 100a, and a p+ type region 100b and a n+ type region 100c which are formed separated from each other at the exposed face of the n- type region. An anode electrode 105 and a cathode electrode 106 are connected by an ohmic contact to the p+ type region 100b and the n+ type region 100c, respectively. In the constitution, when the reverse bias voltage is applied to the pn junction formed between the p+ region 100b and the n- type region 100a by the anode electrode 105 and the cathode electrode 106, a depletion layer is considerably extended to the n- type region side. Since the depth of the semiconductor island 100 is shallow, the depletion layer can not be extended to the perpendicular direction but instead must extend to the lateral direction. In the case shown, the field strength and the equipotential lines are as shown in the figure. An unusually high peak of the field strength appears in the vicinity of the boundary between the n- type region 100a and the n+ type region 100c where the extension of the depletion layer is stopped. Increasing the interval between the p+ type region 100b and the n+ type region 100c can suppress the peak, however, this undesirably makes the semiconductor larger and reduces the integration density.
As mentioned above, by virtue the semiconductor integrated circuit apparatus using the existing dielectric separation substrate, it is impossible to realize a high withstand voltage and a high integration density at the same time since increasing the withstand voltage impedes the high integration density and vice versa. The increasing trend of the commercial power voltage from 100 V to 200 V renders it impossible to avoid the increase of the withstand voltage in the field of the semiconductor integrated circuits using a dielectric separation substrate. The decrease of the integration density of the semiconductor integrated circuit apparatus means the functional deterioration of one-chip circuits and brings about the loss of the largest merit in using an integrated circuit apparatus for an electric circuit.